In conventional multi-chip flip-chip package, a plurality of semiconductor chips are requested to flip-chip mount on a substrate. As disclosed in R.O.C. Taiwan Patent No. 465,803 entitled “multi-chip stacked structure”, a plurality of chips are flip-chip mounted on the top surface and on the bottom surface of the substrate respectively. Since the active surfaces of the chips are turned upside down to face the substrate for bumps connection, therefore, the substrate should be larger enough to provide flip-chip mounting areas for the bumped chips since the bumped chips can not vertically stack on a substrate.
Referring to FIG. 1, a conventional stacked flip-chip package 100 has a face-to-face flip-chip connection. The package 100 comprises a substrate 110, a first chip 120, a second chip 130, and a molding compound 170. The back surface 122 of the first chip 120 is attached to the top surface 111 of the substrate 110 by die-attach material. A plurality of bonding pads 123 and a plurality of redistributed traces 124 are formed on the active surface 121 of the first chip 120. The second chip 130 has a plurality of bumps 140 on its active surface 131. The second chip 130 is flip-chip mounted on the active surface 121 of the first chip 120 via the bumps 140 to electrically connect to the redistributed traces 124. An under-filling material 160 is applied between the active surface 131 of the second chip 130 and the active surface 121 of the first chip 120 to encapsulate the bumps 140. The bonding pads 123 of the first chip 120 and the redistributed traces 124 are electrically connected to the substrate 110 via a plurality of bonding wires 150. An encapsulant 170 is formed on the top surface 111 of the substrate 110 to encapsulate the first chip 120 and the second chip 130 and the bonding wires 150. Besides, a plurality of solder balls 180 are placed on the bottom surface 112 of the substrate 110. When the package 100 is in operation, the heat generated from the first chip 120 and the second chip 130 will accumulate between the first chip 120 and the second chip 130, which can not be easily dissipated. Furthermore, since the plurality of bonding pads 123 and a plurality of redistributed traces 124 are designed on the active surface 121 of the first chip 120, the redistributed traces 124 become quite complicated and jammed. The bonding pads 123 and the wire-connecting pads of the redistributed traces 124 can only be designed at the periphery of the active surface 121, therefore, the electrical performance will be reduced. The conventional stacked face-to-face flip-chip packages similar to the package 100 mentioned above have been disclosed also in U.S. Pat. No. 6,057,598 and R.O.C. Taiwan Patent No. 461,058.